Suggestion
Theoretical impact, if target counter could be changed by -0.2
| Counter | Score | runtime | power_sys | power_cpu | power_mem | Description |
|---|---|---|---|---|---|---|
| PAPI_L2_TCM | -14.90% | 0.00% | -4.04% | -3.63% | -7.23% | Level 2 cache misses |
| PAPI_L1_TCM | -13.87% | 0.00% | -3.35% | -3.01% | -7.51% | Level 1 cache misses |
| PAPI_BR_CN | -11.71% | -11.71% | 0.00% | 0.00% | 0.00% | Conditional branch instructions |
| PAPI_L1_LDM | -8.55% | -8.29% | -0.14% | -0.12% | 0.00% | Level 1 load misses |
| PAPI_L2_DCR | -8.08% | -7.80% | -0.15% | -0.13% | 0.00% | Level 2 data cache reads |
| PAPI_RES_STL | -5.36% | 0.00% | -1.41% | -1.53% | -2.42% | Cycles stalled on any resource |
| PAPI_BR_NTK | -5.03% | 0.00% | -1.39% | -1.48% | -2.16% | Conditional branch instructions not taken |
| PAPI_TLB_IM | -3.04% | 0.00% | -1.47% | -1.57% | 0.00% | Instruction translation lookaside buffer misses |
| PAPI_L2_DCM | -3.00% | 0.00% | -1.44% | -1.56% | 0.00% | Level 2 data cache misses |
| PAPI_SR_INS | -2.99% | 0.00% | -1.45% | -1.54% | 0.00% | Store instructions |
| PAPI_L1_DCM | -2.96% | 0.00% | -1.44% | -1.52% | 0.00% | Level 1 data cache misses |
| PAPI_L2_ICM | -2.78% | 0.00% | -1.35% | -1.44% | 0.00% | Level 2 instruction cache misses |
| PAPI_L2_LDM | -2.40% | 0.00% | -0.96% | -0.99% | -0.46% | Level 2 load misses |
| PAPI_L2_STM | -2.34% | 0.00% | -0.93% | -0.96% | -0.45% | Level 2 store misses |
| PAPI_TOT_INS | -2.18% | 0.00% | -0.58% | -0.86% | -0.73% | Instructions completed |
| PAPI_L2_ICA | -0.78% | 0.00% | -0.29% | -0.30% | -0.19% | Level 2 instruction cache accesses |
| PAPI_L2_TCW | -0.49% | 0.00% | 0.00% | 0.00% | -0.49% | Level 2 total cache writes |