Suggestion
Theoretical impact, if target counter could be changed by -0.2
| Counter | Score | runtime | power_sys | power_cpu | power_mem | Description |
|---|---|---|---|---|---|---|
| PAPI_L3_TCM | -11.62% | 0.00% | -2.45% | -2.96% | -6.22% | Level 3 cache misses |
| PAPI_LD_INS | -11.56% | 0.00% | -2.44% | -2.94% | -6.18% | Load instructions |
| PAPI_L2_TCM | -10.73% | 0.00% | -2.48% | -3.20% | -5.05% | Level 2 cache misses |
| PAPI_L1_TCM | -6.45% | 0.00% | -2.15% | -1.19% | -3.11% | Level 1 cache misses |
| PAPI_TLB_DM | -6.21% | 0.00% | -2.05% | -1.08% | -3.08% | Data translation lookaside buffer misses |
| PAPI_L2_DCA | -6.20% | 0.00% | -2.00% | -1.08% | -3.12% | Level 2 data cache accesses |
| PAPI_L1_ICM | -5.77% | 0.00% | -1.83% | -0.98% | -2.97% | Level 1 instruction cache misses |
| PAPI_L1_STM | -5.15% | 0.00% | -0.34% | -0.18% | -4.63% | Level 1 store misses |
| PAPI_TOT_INS | -3.75% | 0.00% | -1.00% | 0.00% | -2.75% | Instructions completed |
| PAPI_L2_LDM | -2.36% | 0.00% | 0.00% | 0.00% | -2.36% | Level 2 load misses |
| PAPI_BR_NTK | -2.36% | 0.00% | 0.00% | 0.00% | -2.36% | Conditional branch instructions not taken |
| PAPI_L1_LDM | -1.47% | 0.00% | -0.40% | 0.00% | -1.06% | Level 1 load misses |
| PAPI_RES_STL | +8.88% | 0.00% | +2.08% | +2.68% | +4.13% | Cycles stalled on any resource |