Suggestion
Theoretical impact, if target counter could be changed by -0.2
| Counter | Score | runtime | power_sys | power_cpu | power_mem | Description |
|---|---|---|---|---|---|---|
| PAPI_LD_INS | -12.06% | 0.00% | -2.76% | -2.85% | -6.45% | Load instructions |
| PAPI_L2_TCM | -9.69% | 0.00% | -3.00% | -3.23% | -3.46% | Level 2 cache misses |
| PAPI_L3_TCM | -6.88% | 0.00% | -0.61% | -0.11% | -6.16% | Level 3 cache misses |
| PAPI_L1_STM | -6.63% | 0.00% | -0.58% | -0.10% | -5.96% | Level 1 store misses |
| PAPI_TLB_DM | -6.47% | 0.00% | -2.62% | -1.56% | -2.30% | Data translation lookaside buffer misses |
| PAPI_L2_DCA | -6.39% | 0.00% | -2.57% | -1.53% | -2.29% | Level 2 data cache accesses |
| PAPI_L1_TCM | -6.34% | 0.00% | -2.49% | -1.48% | -2.36% | Level 1 cache misses |
| PAPI_L1_LDM | -5.71% | 0.00% | -2.31% | -1.37% | -2.03% | Level 1 load misses |
| PAPI_TOT_INS | -4.46% | 0.00% | -0.66% | 0.00% | -3.80% | Instructions completed |
| PAPI_L2_TCW | -2.09% | 0.00% | 0.00% | 0.00% | -2.09% | Level 2 total cache writes |
| PAPI_TLB_IM | -0.06% | -0.06% | 0.00% | 0.00% | 0.00% | Instruction translation lookaside buffer misses |
| PAPI_RES_STL | +7.82% | 0.00% | +2.49% | +2.72% | +2.60% | Cycles stalled on any resource |