Suggestion
Theoretical impact, if target counter could be changed by -0.2
| Counter | Score | runtime | power_sys | power_cpu | power_mem | Description |
|---|---|---|---|---|---|---|
| PAPI_L2_TCM | -12.85% | 0.00% | -2.65% | -3.31% | -6.89% | Level 2 cache misses |
| PAPI_LD_INS | -12.68% | 0.00% | -2.57% | -3.17% | -6.94% | Load instructions |
| PAPI_L3_TCM | -11.75% | 0.00% | -2.33% | -2.85% | -6.57% | Level 3 cache misses |
| PAPI_L2_ICA | -6.20% | 0.00% | 0.00% | 0.00% | -6.20% | Level 2 instruction cache accesses |
| PAPI_L1_TCM | -4.23% | 0.00% | -2.51% | -1.12% | -0.59% | Level 1 cache misses |
| PAPI_L2_DCA | -3.82% | +0.04% | -2.27% | -1.01% | -0.58% | Level 2 data cache accesses |
| PAPI_TLB_IM | +0.70% | -0.04% | 0.00% | 0.00% | +0.73% | Instruction translation lookaside buffer misses |
| PAPI_RES_STL | +11.48% | 0.00% | +2.35% | +2.92% | +6.21% | Cycles stalled on any resource |