Suggestion
Theoretical impact, if target counter could be changed by -0.2
| Counter | Score | runtime | power_sys | power_cpu | power_mem | Description |
|---|---|---|---|---|---|---|
| PAPI_L2_TCM | -18.52% | +0.01% | -4.68% | -4.52% | -9.34% | Level 2 cache misses |
| PAPI_L2_DCA | -17.64% | 0.00% | -4.45% | -4.31% | -8.89% | Level 2 data cache accesses |
| PAPI_L1_LDM | -17.62% | 0.00% | -3.95% | -3.37% | -10.30% | Level 1 load misses |
| PAPI_L1_ICM | -16.98% | 0.00% | -4.33% | -3.74% | -8.90% | Level 1 instruction cache misses |
| PAPI_L1_TCM | -14.70% | 0.00% | -4.22% | -4.29% | -6.19% | Level 1 cache misses |
| PAPI_CA_ITV | -4.26% | 0.00% | 0.00% | -0.11% | -4.15% | Requests for cache line intervention |
| PAPI_L1_STM | -2.03% | 0.00% | +0.10% | -0.10% | -2.04% | Level 1 store misses |
| PAPI_TOT_INS | -1.18% | 0.00% | -1.18% | 0.00% | 0.00% | Instructions completed |
| PAPI_L2_TCW | -0.84% | 0.00% | 0.00% | -0.01% | -0.83% | Level 2 total cache writes |
| PAPI_L2_ICM | -0.02% | -0.02% | 0.00% | 0.00% | 0.00% | Level 2 instruction cache misses |
| PAPI_SR_INS | +13.21% | -0.02% | +3.58% | +3.20% | +6.46% | Store instructions |
| PAPI_L1_DCM | +14.02% | -0.02% | +3.80% | +3.39% | +6.85% | Level 1 data cache misses |
| PAPI_RES_STL | +20.99% | 0.00% | +4.22% | +4.08% | +12.69% | Cycles stalled on any resource |