Suggestion
Theoretical impact, if target counter could be changed by -0.2
| Counter | Score | runtime | power_sys | power_cpu | power_mem | Description |
|---|---|---|---|---|---|---|
| PAPI_TOT_INS | -18.96% | -1.23% | -5.84% | -4.42% | -7.47% | Instructions completed |
| PAPI_L2_DCM | -17.73% | -1.82% | -6.57% | -4.79% | -4.55% | Level 2 data cache misses |
| PAPI_L2_ICA | -15.86% | -5.83% | -4.26% | -5.78% | 0.00% | Level 2 instruction cache accesses |
| PAPI_L1_STM | -15.18% | -4.85% | -2.08% | -2.30% | -5.94% | Level 1 store misses |
| PAPI_RES_STL | -15.12% | -6.70% | -3.57% | -4.85% | 0.00% | Cycles stalled on any resource |
| PAPI_L1_TCM | -5.82% | -1.31% | -2.27% | -2.24% | 0.00% | Level 1 cache misses |
| PAPI_TLB_DM | -5.67% | -1.49% | -1.92% | -2.26% | 0.00% | Data translation lookaside buffer misses |
| PAPI_L2_TCW | -3.49% | +2.33% | -1.71% | -0.05% | -4.07% | Level 2 total cache writes |
| PAPI_L2_LDM | -3.20% | +2.28% | -1.77% | -0.10% | -3.61% | Level 2 load misses |
| PAPI_L2_STM | +1.82% | -2.46% | +1.30% | -0.42% | +3.40% | Level 2 store misses |
| PAPI_BR_CN | +4.06% | +1.63% | -2.63% | -1.17% | +6.23% | Conditional branch instructions |
| PAPI_L1_LDM | +14.59% | +3.62% | +1.79% | +3.04% | +6.13% | Level 1 load misses |