Suggestion
Theoretical impact, if target counter could be changed by -0.2
| Counter | Score | runtime | power_sys | power_cpu | power_mem | Description |
|---|---|---|---|---|---|---|
| PAPI_L1_TCM | -16.02% | 0.00% | -4.09% | -3.80% | -8.13% | Level 1 cache misses |
| PAPI_L2_TCM | -15.71% | 0.00% | -4.36% | -4.00% | -7.34% | Level 2 cache misses |
| PAPI_BR_CN | -10.38% | -10.38% | 0.00% | 0.00% | 0.00% | Conditional branch instructions |
| PAPI_L1_LDM | -6.48% | -6.48% | 0.00% | 0.00% | 0.00% | Level 1 load misses |
| PAPI_RES_STL | -4.31% | 0.00% | -1.20% | -1.26% | -1.85% | Cycles stalled on any resource |
| PAPI_BR_NTK | -4.14% | 0.00% | -1.21% | -1.30% | -1.63% | Conditional branch instructions not taken |
| PAPI_L2_LDM | -3.04% | 0.00% | -1.08% | -1.11% | -0.84% | Level 2 load misses |
| PAPI_TLB_IM | -2.99% | 0.00% | -1.45% | -1.54% | 0.00% | Instruction translation lookaside buffer misses |
| PAPI_SR_INS | -2.92% | 0.00% | -1.42% | -1.50% | 0.00% | Store instructions |
| PAPI_L1_DCM | -2.91% | 0.00% | -1.42% | -1.49% | 0.00% | Level 1 data cache misses |
| PAPI_L2_DCM | -2.88% | 0.00% | -1.39% | -1.48% | 0.00% | Level 2 data cache misses |
| PAPI_L3_TCM | -2.51% | -2.51% | 0.00% | 0.00% | 0.00% | Level 3 cache misses |
| PAPI_TOT_INS | -1.74% | 0.00% | -0.36% | -0.62% | -0.76% | Instructions completed |
| PAPI_L2_ICA | -0.70% | 0.00% | -0.32% | -0.38% | 0.00% | Level 2 instruction cache accesses |
| PAPI_LD_INS | -0.63% | -0.63% | 0.00% | 0.00% | 0.00% | Load instructions |