Suggestion
Theoretical impact, if target counter could be changed by -0.2
| Counter | Score | runtime | power_sys | power_cpu | power_mem | Description |
|---|---|---|---|---|---|---|
| PAPI_L2_TCM | -11.24% | -1.13% | -2.26% | 0.00% | -7.85% | Level 2 cache misses |
| PAPI_L1_TCM | -9.09% | 0.00% | -2.15% | -1.65% | -5.28% | Level 1 cache misses |
| PAPI_L2_DCR | -8.18% | 0.00% | -2.20% | -1.47% | -4.52% | Level 2 data cache reads |
| PAPI_BR_NTK | -6.17% | -2.03% | -0.61% | -0.57% | -2.96% | Conditional branch instructions not taken |
| PAPI_BR_MSP | -3.64% | -0.17% | -0.38% | -0.11% | -2.98% | Conditional branch instructions mispredicted |
| PAPI_RES_STL | -3.45% | -2.60% | -0.28% | -0.57% | 0.00% | Cycles stalled on any resource |
| PAPI_L2_ICA | -2.73% | -2.05% | -0.23% | -0.46% | 0.00% | Level 2 instruction cache accesses |
| PAPI_CA_ITV | -2.59% | 0.00% | -1.05% | -1.54% | 0.00% | Requests for cache line intervention |
| PAPI_L3_TCM | -2.29% | 0.00% | -0.61% | 0.00% | -1.68% | Level 3 cache misses |
| PAPI_CA_SHR | -2.13% | 0.00% | 0.00% | -1.18% | -0.96% | Requests for exclusive access to shared cache line |
| PAPI_LD_INS | -1.73% | -1.73% | 0.00% | 0.00% | 0.00% | Load instructions |
| PAPI_TOT_INS | -1.64% | 0.00% | -0.27% | 0.00% | -1.37% | Instructions completed |
| PAPI_SR_INS | -0.74% | 0.00% | -0.39% | -0.35% | 0.00% | Store instructions |
| PAPI_L2_STM | -0.56% | -0.55% | -0.01% | 0.00% | 0.00% | Level 2 store misses |
| PAPI_L2_ICM | -0.47% | 0.00% | -0.21% | -0.26% | 0.00% | Level 2 instruction cache misses |
| PAPI_TLB_IM | -0.45% | 0.00% | -0.40% | -0.06% | 0.00% | Instruction translation lookaside buffer misses |
| PAPI_L1_DCM | -0.40% | 0.00% | -0.35% | -0.05% | 0.00% | Level 1 data cache misses |
| PAPI_L1_STM | -0.23% | 0.00% | 0.00% | -0.23% | 0.00% | Level 1 store misses |