Suggestion
Theoretical impact, if target counter could be changed by -0.2
| Counter | Score | runtime | power_sys | power_cpu | power_mem | Description |
|---|---|---|---|---|---|---|
| PAPI_L2_TCM | -13.21% | -2.53% | -1.66% | 0.00% | -9.01% | Level 2 cache misses |
| PAPI_LD_INS | -11.35% | -2.66% | -1.35% | 0.00% | -7.34% | Load instructions |
| PAPI_L1_TCM | -8.19% | 0.00% | -2.63% | -2.20% | -3.35% | Level 1 cache misses |
| PAPI_L2_DCW | -8.08% | 0.00% | -2.49% | -2.08% | -3.52% | Level 2 data cache writes |
| PAPI_TLB_DM | -7.73% | 0.00% | -2.35% | -1.97% | -3.41% | Data translation lookaside buffer misses |
| PAPI_CA_ITV | -4.90% | 0.00% | -2.25% | -2.66% | 0.00% | Requests for cache line intervention |
| PAPI_RES_STL | -4.86% | -2.24% | -0.43% | -0.26% | -1.93% | Cycles stalled on any resource |
| PAPI_BR_NTK | -4.83% | -1.88% | -0.39% | -0.21% | -2.34% | Conditional branch instructions not taken |
| PAPI_BR_MSP | -4.79% | -1.83% | -0.39% | -0.21% | -2.36% | Conditional branch instructions mispredicted |
| PAPI_L3_TCM | -3.59% | 0.00% | -1.03% | -1.04% | -1.52% | Level 3 cache misses |
| PAPI_TOT_INS | -2.84% | -0.27% | -0.66% | 0.00% | -1.91% | Instructions completed |
| PAPI_L1_STM | -1.64% | -0.25% | 0.00% | 0.00% | -1.39% | Level 1 store misses |
| PAPI_L2_ICA | -0.47% | -0.47% | 0.00% | 0.00% | 0.00% | Level 2 instruction cache accesses |
| PAPI_L2_ICM | -0.31% | 0.00% | -0.15% | -0.17% | 0.00% | Level 2 instruction cache misses |
| PAPI_L2_STM | -0.31% | -0.31% | 0.00% | 0.00% | 0.00% | Level 2 store misses |