Suggestion
Theoretical impact, if target counter could be changed by -0.2
| Counter | Score | runtime | power_sys | power_cpu | power_mem | Description |
|---|---|---|---|---|---|---|
| PAPI_L2_TCM | -15.25% | 0.00% | -4.32% | -4.31% | -6.61% | Level 2 cache misses |
| PAPI_L1_TCM | -15.02% | 0.00% | -4.53% | -3.56% | -6.93% | Level 1 cache misses |
| PAPI_L3_TCM | -11.80% | 0.00% | -2.54% | -3.08% | -6.18% | Level 3 cache misses |
| PAPI_TOT_INS | -7.44% | 0.00% | -2.69% | -0.78% | -3.97% | Instructions completed |
| PAPI_L2_DCA | -5.03% | 0.00% | -1.82% | -0.86% | -2.35% | Level 2 data cache accesses |
| PAPI_L1_STM | -4.86% | 0.00% | -0.66% | -0.31% | -3.90% | Level 1 store misses |
| PAPI_L2_ICA | -3.58% | 0.00% | 0.00% | 0.00% | -3.58% | Level 2 instruction cache accesses |
| PAPI_BR_NTK | -3.27% | 0.00% | 0.00% | 0.00% | -3.27% | Conditional branch instructions not taken |
| PAPI_L2_STM | -2.55% | 0.00% | 0.00% | 0.00% | -2.55% | Level 2 store misses |
| PAPI_L1_ICM | -0.95% | 0.00% | 0.00% | 0.00% | -0.95% | Level 1 instruction cache misses |
| PAPI_L1_LDM | -0.84% | 0.00% | 0.00% | 0.00% | -0.84% | Level 1 load misses |
| PAPI_RES_STL | +9.19% | 0.00% | +2.20% | +2.86% | +4.14% | Cycles stalled on any resource |