Suggestion
Theoretical impact, if target counter could be changed by -0.2
| Counter | Score | runtime | power_sys | power_cpu | power_mem | Description |
|---|---|---|---|---|---|---|
| PAPI_LD_INS | -28.45% | -19.13% | -2.27% | -7.04% | 0.00% | Load instructions |
| PAPI_SR_INS | -28.05% | -18.82% | -2.31% | -6.92% | 0.00% | Store instructions |
| PAPI_L2_TCM | -12.90% | 0.00% | -12.90% | 0.00% | 0.00% | Level 2 cache misses |
| PAPI_L1_LDM | -10.33% | 0.00% | 0.00% | 0.00% | -10.33% | Level 1 load misses |
| PAPI_L2_TCH | -8.81% | 0.00% | 0.00% | -12.15% | +3.34% | Level 2 total cache hits |
| PAPI_L1_ICA | -5.42% | 0.00% | 0.00% | +0.68% | -6.10% | Level 1 instruction cache accesses |
| PAPI_L1_ICM | -4.75% | 0.00% | -4.75% | 0.00% | 0.00% | Level 1 instruction cache misses |
| PAPI_RES_STL | -0.86% | -0.86% | 0.00% | 0.00% | 0.00% | Cycles stalled on any resource |
| PAPI_L2_LDM | +4.39% | 0.00% | 0.00% | -0.80% | +5.19% | Level 2 load misses |
| PAPI_BR_MSP | +7.81% | 0.00% | 0.00% | +11.35% | -3.54% | Conditional branch instructions mispredicted |