Suggestion
Theoretical impact, if target counter could be changed by -0.2
| Counter | Score | runtime | power_sys | power_cpu | power_mem | Description |
|---|---|---|---|---|---|---|
| PAPI_RES_STL | -9.22% | +0.68% | -0.89% | -1.73% | -7.28% | Cycles stalled on any resource |
| PAPI_VEC_INS | -6.87% | 0.00% | -1.85% | -2.90% | -2.13% | Vector/SIMD instructions (could include integer) |
| PAPI_L1_TCM | -6.20% | 0.00% | -0.61% | 0.00% | -5.59% | Level 1 cache misses |
| PAPI_BR_TKN | -5.71% | -4.25% | 0.00% | -0.61% | -0.86% | Conditional branch instructions taken |
| PAPI_L1_ICM | -5.50% | -4.16% | 0.00% | -0.56% | -0.78% | Level 1 instruction cache misses |
| PAPI_L2_ICA | -5.46% | -4.13% | 0.00% | -0.55% | -0.77% | Level 2 instruction cache accesses |
| PAPI_TLB_IM | -5.42% | -4.13% | 0.00% | -0.54% | -0.76% | Instruction translation lookaside buffer misses |
| PAPI_TLB_DM | -5.20% | -3.95% | 0.00% | -0.52% | -0.73% | Data translation lookaside buffer misses |
| PAPI_L1_ICA | -2.98% | +2.56% | -0.49% | +0.61% | -5.66% | Level 1 instruction cache accesses |
| PAPI_BR_INS | -0.94% | -4.31% | 0.00% | -0.63% | +4.00% | Branch instructions |
| PAPI_L2_ICM | -0.76% | -4.14% | 0.00% | -0.59% | +3.97% | Level 2 instruction cache misses |
| PAPI_BR_NTK | -0.57% | -4.18% | 0.00% | -0.65% | +4.26% | Conditional branch instructions not taken |
| PAPI_CA_SHR | -0.26% | 0.00% | -0.26% | 0.00% | 0.00% | Requests for exclusive access to shared cache line |
| PAPI_CA_CLN | -0.15% | 0.00% | 0.00% | 0.00% | -0.15% | Requests for exclusive access to clean cache line |
| PAPI_SR_INS | +8.23% | -0.73% | +0.83% | +1.58% | +6.55% | Store instructions |