Suggestion
Theoretical impact, if target counter could be changed by -0.2
| Counter | Score | runtime | power_sys | power_cpu | power_mem | Description |
|---|---|---|---|---|---|---|
| PAPI_BR_INS | -6.27% | +8.83% | -6.13% | -3.26% | -5.72% | Branch instructions |
| PAPI_RES_STL | -4.85% | +12.96% | -4.76% | -3.83% | -9.23% | Cycles stalled on any resource |
| PAPI_SR_INS | -2.89% | +6.33% | -3.73% | -3.67% | -1.82% | Store instructions |
| PAPI_BR_MSP | -2.78% | +6.31% | -3.67% | -3.58% | -1.84% | Conditional branch instructions mispredicted |
| PAPI_BR_TKN | -1.81% | +7.06% | -3.53% | -3.39% | -1.94% | Conditional branch instructions taken |
| PAPI_L1_DCA | -1.64% | +7.13% | -3.51% | -3.32% | -1.93% | Level 1 data cache accesses |
| PAPI_L2_TCA | -0.51% | -8.27% | +3.03% | +2.78% | +1.94% | Level 2 total cache accesses |
| PAPI_BR_NTK | +1.41% | +12.41% | -4.29% | -4.07% | -2.65% | Conditional branch instructions not taken |
| PAPI_TLB_DM | +15.73% | -9.31% | +9.77% | +9.40% | +5.87% | Data translation lookaside buffer misses |
| PAPI_L2_TCM | +15.75% | -9.44% | +9.83% | +9.47% | +5.89% | Level 2 cache misses |
| PAPI_L2_LDM | +15.80% | -9.54% | +9.87% | +9.50% | +5.96% | Level 2 load misses |