Suggestion
Theoretical impact, if target counter could be changed by -0.2
| Counter | Score | runtime | power_sys | power_cpu | power_mem | Description |
|---|---|---|---|---|---|---|
| PAPI_L1_TCA | -8.42% | +6.95% | -5.72% | +0.97% | -10.62% | Level 1 total cache accesses |
| PAPI_L2_ICA | -8.32% | -5.93% | -1.01% | -1.05% | -0.33% | Level 2 instruction cache accesses |
| PAPI_L1_ICM | -8.30% | -5.88% | -1.02% | -1.07% | -0.34% | Level 1 instruction cache misses |
| PAPI_BR_TKN | -7.89% | +6.60% | -5.64% | +0.92% | -9.77% | Conditional branch instructions taken |
| PAPI_FP_INS | -3.37% | -2.00% | -0.02% | 0.00% | -1.36% | Floating point instructions |
| PAPI_FP_OPS | -3.37% | -2.00% | -0.02% | 0.00% | -1.36% | Floating point operations |
| PAPI_L2_STM | -3.33% | -1.81% | -0.02% | 0.00% | -1.50% | Level 2 store misses |
| PAPI_FDV_INS | -3.28% | -1.77% | -0.02% | 0.00% | -1.49% | Floating point divide instructions |
| PAPI_RES_STL | -1.83% | +0.10% | 0.00% | -1.93% | 0.00% | Cycles stalled on any resource |
| PAPI_TLB_DM | -0.09% | 0.00% | -0.02% | -0.06% | -0.01% | Data translation lookaside buffer misses |
| PAPI_BR_NTK | +1.49% | -0.12% | 0.00% | +1.61% | 0.00% | Conditional branch instructions not taken |
| PAPI_L2_TCW | +7.42% | -7.16% | +5.46% | -0.99% | +10.12% | Level 2 total cache writes |
| PAPI_L1_STM | +7.42% | -7.16% | +5.46% | -0.99% | +10.12% | Level 1 store misses |
| PAPI_L2_DCW | +7.45% | -7.14% | +5.46% | -0.99% | +10.12% | Level 2 data cache writes |