Suggestion
Theoretical impact, if target counter could be changed by -0.2
| Counter | Score | runtime | power_sys | power_cpu | power_mem | Description |
|---|---|---|---|---|---|---|
| PAPI_L2_ICM | -17.28% | -3.39% | -5.46% | -6.50% | -1.92% | Level 2 instruction cache misses |
| PAPI_L1_DCM | -17.03% | -3.50% | -5.29% | -6.30% | -1.94% | Level 1 data cache misses |
| PAPI_L3_TCM | -16.89% | -3.04% | -5.35% | -6.37% | -2.14% | Level 3 cache misses |
| PAPI_RES_STL | -11.52% | -1.42% | -3.86% | -4.76% | -1.49% | Cycles stalled on any resource |
| PAPI_BR_NTK | -10.30% | -1.84% | -3.23% | -3.98% | -1.25% | Conditional branch instructions not taken |
| PAPI_L2_TCA | -2.99% | -2.99% | 0.00% | 0.00% | 0.00% | Level 2 total cache accesses |
| PAPI_L1_LDM | -0.94% | -0.94% | 0.00% | 0.00% | 0.00% | Level 1 load misses |
| PAPI_L1_ICM | +7.88% | -0.80% | +3.31% | +4.09% | +1.28% | Level 1 instruction cache misses |