Suggestion
Theoretical impact, if target counter could be changed by -0.2
| Counter | Score | runtime | power_sys | power_cpu | power_mem | Description |
|---|---|---|---|---|---|---|
| PAPI_L2_DCA | -11.88% | -0.27% | -0.63% | 0.00% | -10.98% | Level 2 data cache accesses |
| PAPI_TLB_DM | -11.44% | -0.26% | -0.66% | 0.00% | -10.52% | Data translation lookaside buffer misses |
| PAPI_L1_STM | -0.62% | -0.02% | -0.19% | -0.02% | -0.39% | Level 1 store misses |
| PAPI_CA_CLN | -0.46% | 0.00% | -0.46% | 0.00% | 0.00% | Requests for exclusive access to clean cache line |
| PAPI_BR_NTK | -0.35% | 0.00% | -0.07% | 0.00% | -0.28% | Conditional branch instructions not taken |
| PAPI_L3_TCM | -0.25% | 0.00% | -0.25% | 0.00% | 0.00% | Level 3 cache misses |
| PAPI_RES_STL | -0.21% | 0.00% | -0.10% | -0.11% | 0.00% | Cycles stalled on any resource |
| PAPI_TOT_INS | -0.16% | 0.00% | -0.09% | -0.07% | 0.00% | Instructions completed |
| PAPI_L2_TCM | -0.10% | -0.10% | 0.00% | 0.00% | 0.00% | Level 2 cache misses |
| PAPI_L2_ICA | -0.03% | -0.03% | 0.00% | 0.00% | 0.00% | Level 2 instruction cache accesses |
| PAPI_L2_ICM | -0.01% | -0.01% | 0.00% | 0.00% | 0.00% | Level 2 instruction cache misses |
| PAPI_L1_TCM | -0.01% | -0.01% | 0.00% | 0.00% | 0.00% | Level 1 cache misses |