Suggestion
Theoretical impact, if target counter could be changed by -0.2
| Counter | Score | runtime | power_sys | power_cpu | power_mem | Description |
|---|---|---|---|---|---|---|
| PAPI_L2_TCM | -12.67% | +0.48% | -2.48% | -3.17% | -7.50% | Level 2 cache misses |
| PAPI_CA_SHR | -12.46% | +0.50% | -2.51% | -3.17% | -7.28% | Requests for exclusive access to shared cache line |
| PAPI_BR_CN | -11.02% | +0.44% | -2.50% | -3.36% | -5.60% | Conditional branch instructions |
| PAPI_CA_ITV | -10.98% | +0.49% | -2.57% | -3.26% | -5.65% | Requests for cache line intervention |
| PAPI_L3_TCM | -6.61% | 0.00% | -0.15% | -0.71% | -5.74% | Level 3 cache misses |
| PAPI_L1_STM | -3.21% | -2.37% | 0.00% | 0.00% | -0.84% | Level 1 store misses |
| PAPI_BR_INS | -2.95% | 0.00% | -0.66% | -0.59% | -1.70% | Branch instructions |
| PAPI_TOT_INS | -1.19% | 0.00% | -0.12% | -0.33% | -0.74% | Instructions completed |
| PAPI_BR_NTK | -0.99% | 0.00% | -0.10% | -0.27% | -0.62% | Conditional branch instructions not taken |
| PAPI_L1_LDM | -0.85% | 0.00% | 0.00% | 0.00% | -0.85% | Level 1 load misses |
| PAPI_BR_TKN | -0.48% | 0.00% | 0.00% | -0.48% | 0.00% | Conditional branch instructions taken |
| PAPI_L2_STM | -0.12% | 0.00% | 0.00% | -0.12% | 0.00% | Level 2 store misses |
| PAPI_RES_STL | +6.57% | -0.44% | +1.56% | +1.80% | +3.65% | Cycles stalled on any resource |
| PAPI_L2_ICA | +9.85% | +1.93% | +1.59% | +2.04% | +4.29% | Level 2 instruction cache accesses |
| PAPI_TLB_IM | +10.52% | -0.52% | +2.41% | +3.06% | +5.57% | Instruction translation lookaside buffer misses |