Suggestion
Theoretical impact, if target counter could be changed by -0.2
| Counter | Score | runtime | power_sys | power_cpu | power_mem | Description |
|---|---|---|---|---|---|---|
| PAPI_L1_LDM | -12.59% | -12.59% | 0.00% | 0.00% | 0.00% | Level 1 load misses |
| PAPI_CA_CLN | -8.96% | 0.00% | 0.00% | -4.02% | -4.94% | Requests for exclusive access to clean cache line |
| PAPI_L2_DCA | -8.78% | 0.00% | 0.00% | -4.57% | -4.21% | Level 2 data cache accesses |
| PAPI_L2_STM | -7.53% | -5.76% | -0.22% | -1.25% | -0.30% | Level 2 store misses |
| PAPI_L1_TCM | -5.76% | 0.00% | 0.00% | -1.59% | -4.17% | Level 1 cache misses |
| PAPI_SR_INS | -3.97% | 0.00% | -1.74% | -1.30% | -0.93% | Store instructions |
| PAPI_TLB_IM | -3.96% | 0.00% | -1.74% | -1.29% | -0.92% | Instruction translation lookaside buffer misses |
| PAPI_L1_DCM | -3.91% | 0.00% | -1.72% | -1.27% | -0.92% | Level 1 data cache misses |
| PAPI_L2_DCM | -3.81% | 0.00% | -1.68% | -1.24% | -0.88% | Level 2 data cache misses |
| PAPI_BR_TKN | -3.47% | 0.00% | 0.00% | -1.14% | -2.33% | Conditional branch instructions taken |
| PAPI_BR_INS | -1.59% | -1.59% | 0.00% | 0.00% | 0.00% | Branch instructions |
| PAPI_L1_STM | -1.57% | 0.00% | -1.57% | 0.00% | 0.00% | Level 1 store misses |
| PAPI_RES_STL | -0.46% | 0.00% | 0.00% | -0.34% | -0.12% | Cycles stalled on any resource |
| PAPI_TOT_INS | -0.02% | -0.02% | 0.00% | 0.00% | 0.00% | Instructions completed |