Suggestion
Theoretical impact, if target counter could be changed by -0.2
| Counter | Score | runtime | power_sys | power_cpu | power_mem | Description |
|---|---|---|---|---|---|---|
| PAPI_L2_DCA | -8.30% | 0.00% | 0.00% | 0.00% | -8.30% | Level 2 data cache accesses |
| PAPI_TLB_DM | -7.88% | 0.00% | 0.00% | 0.00% | -7.88% | Data translation lookaside buffer misses |
| PAPI_TOT_INS | -4.53% | 0.00% | -2.52% | -2.01% | 0.00% | Instructions completed |
| PAPI_BR_INS | -4.49% | -0.07% | -1.52% | -2.90% | 0.00% | Branch instructions |
| PAPI_L2_LDM | -3.03% | -0.00% | -1.70% | -1.00% | -0.33% | Level 2 load misses |
| PAPI_L1_TCM | -2.97% | 0.00% | -2.15% | -0.65% | -0.18% | Level 1 cache misses |
| PAPI_L2_STM | -2.84% | -0.00% | -1.57% | -0.90% | -0.37% | Level 2 store misses |
| PAPI_L1_LDM | -2.78% | 0.00% | -1.80% | -0.77% | -0.21% | Level 1 load misses |
| PAPI_TLB_IM | -2.51% | 0.00% | -1.78% | 0.00% | -0.73% | Instruction translation lookaside buffer misses |
| PAPI_RES_STL | -1.62% | -0.00% | -0.84% | -0.62% | -0.15% | Cycles stalled on any resource |
| PAPI_L1_STM | -1.27% | 0.00% | 0.00% | 0.00% | -1.27% | Level 1 store misses |
| PAPI_L2_ICA | -0.48% | 0.00% | -0.13% | 0.00% | -0.35% | Level 2 instruction cache accesses |
| PAPI_L2_DCR | -0.25% | 0.00% | 0.00% | 0.00% | -0.25% | Level 2 data cache reads |
| PAPI_BR_NTK | -0.08% | -0.01% | 0.00% | 0.00% | -0.07% | Conditional branch instructions not taken |
| PAPI_BR_MSP | -0.08% | -0.01% | 0.00% | 0.00% | -0.07% | Conditional branch instructions mispredicted |
| PAPI_L2_TCM | -0.07% | -0.07% | 0.00% | 0.00% | 0.00% | Level 2 cache misses |
| PAPI_BR_CN | -0.02% | -0.02% | 0.00% | 0.00% | 0.00% | Conditional branch instructions |