Suggestion
Theoretical impact, if target counter could be changed by -0.2
| Counter | Score | runtime | power_sys | power_cpu | power_mem | Description |
|---|---|---|---|---|---|---|
| PAPI_L2_TCM | -11.24% | -0.73% | -2.16% | 0.00% | -8.35% | Level 2 cache misses |
| PAPI_L1_TCM | -8.25% | 0.00% | -1.71% | -1.13% | -5.41% | Level 1 cache misses |
| PAPI_L2_DCR | -6.99% | 0.00% | -1.65% | -0.93% | -4.41% | Level 2 data cache reads |
| PAPI_BR_INS | -6.90% | 0.00% | -1.64% | -0.92% | -4.34% | Branch instructions |
| PAPI_BR_NTK | -4.87% | -1.40% | -0.56% | -0.59% | -2.33% | Conditional branch instructions not taken |
| PAPI_RES_STL | -4.84% | -1.61% | -0.62% | -0.71% | -1.89% | Cycles stalled on any resource |
| PAPI_BR_MSP | -4.75% | -1.28% | -0.55% | -0.57% | -2.35% | Conditional branch instructions mispredicted |
| PAPI_CA_ITV | -2.62% | 0.00% | -0.98% | -1.64% | 0.00% | Requests for cache line intervention |
| PAPI_L3_TCM | -2.57% | 0.00% | -0.74% | 0.00% | -1.83% | Level 3 cache misses |
| PAPI_TOT_INS | -2.55% | -0.61% | 0.00% | 0.00% | -1.94% | Instructions completed |
| PAPI_L2_ICA | -2.40% | -1.39% | -0.43% | -0.59% | 0.00% | Level 2 instruction cache accesses |
| PAPI_L1_STM | -1.47% | 0.00% | -0.49% | -0.90% | -0.08% | Level 1 store misses |
| PAPI_L2_STM | -1.44% | -1.44% | 0.00% | 0.00% | 0.00% | Level 2 store misses |
| PAPI_LD_INS | -1.20% | -1.20% | 0.00% | 0.00% | 0.00% | Load instructions |
| PAPI_CA_SHR | -1.08% | 0.00% | 0.00% | -1.06% | -0.01% | Requests for exclusive access to shared cache line |
| PAPI_SR_INS | -0.81% | 0.00% | -0.44% | -0.37% | 0.00% | Store instructions |
| PAPI_L2_ICM | -0.52% | 0.00% | -0.23% | -0.29% | 0.00% | Level 2 instruction cache misses |
| PAPI_TLB_IM | -0.36% | 0.00% | -0.35% | -0.01% | 0.00% | Instruction translation lookaside buffer misses |