Suggestion
Theoretical impact, if target counter could be changed by -0.2
| Counter | Score | runtime | power_sys | power_cpu | power_mem | Description |
|---|---|---|---|---|---|---|
| PAPI_CA_SHR | -7.89% | -0.12% | -1.77% | -1.29% | -4.71% | Requests for exclusive access to shared cache line |
| PAPI_BR_TKN | -5.52% | 0.00% | 0.00% | 0.00% | -5.52% | Conditional branch instructions taken |
| PAPI_L2_TCM | -4.14% | 0.00% | -0.55% | -0.05% | -3.55% | Level 2 cache misses |
| PAPI_LD_INS | -3.53% | 0.00% | -1.62% | -1.91% | 0.00% | Load instructions |
| PAPI_L2_STM | -1.46% | -0.04% | -0.33% | -0.19% | -0.90% | Level 2 store misses |
| PAPI_L1_STM | -0.93% | -0.07% | -0.38% | -0.49% | 0.00% | Level 1 store misses |
| PAPI_BR_MSP | -0.46% | 0.00% | -0.22% | -0.21% | -0.04% | Conditional branch instructions mispredicted |
| PAPI_BR_CN | -0.07% | -0.07% | 0.00% | 0.00% | 0.00% | Conditional branch instructions |
| PAPI_SR_INS | -0.04% | -0.04% | 0.00% | 0.00% | 0.00% | Store instructions |
| PAPI_L3_TCM | -0.02% | -0.01% | 0.00% | 0.00% | -0.01% | Level 3 cache misses |