Suggestion
Theoretical impact, if target counter could be changed by -0.2
| Counter | Score | runtime | power_sys | power_cpu | power_mem | Description |
|---|---|---|---|---|---|---|
| PAPI_L1_TCA | -10.02% | +6.38% | -6.37% | +0.36% | -10.38% | Level 1 total cache accesses |
| PAPI_RES_STL | -9.34% | +0.31% | -2.74% | -3.87% | -3.04% | Cycles stalled on any resource |
| PAPI_SR_INS | -9.05% | +5.85% | -5.72% | +0.33% | -9.50% | Store instructions |
| PAPI_L1_ICM | -8.12% | -5.39% | -0.89% | -1.09% | -0.75% | Level 1 instruction cache misses |
| PAPI_L2_ICA | -8.02% | -5.40% | -0.86% | -1.05% | -0.72% | Level 2 instruction cache accesses |
| PAPI_L2_STM | -3.59% | -0.90% | -0.44% | -0.23% | -2.02% | Level 2 store misses |
| PAPI_FML_INS | -3.57% | -0.98% | -0.48% | -0.25% | -1.87% | Floating point multiply instructions |
| PAPI_FDV_INS | -3.57% | -0.89% | -0.44% | -0.23% | -2.01% | Floating point divide instructions |
| PAPI_FP_INS | -3.57% | -0.98% | -0.48% | -0.25% | -1.86% | Floating point instructions |
| PAPI_TLB_DM | -0.09% | 0.00% | -0.00% | -0.08% | -0.00% | Data translation lookaside buffer misses |
| PAPI_BR_NTK | +7.61% | -0.37% | +2.27% | +3.20% | +2.51% | Conditional branch instructions not taken |
| PAPI_L1_STM | +8.94% | -6.58% | +6.02% | -0.37% | +9.87% | Level 1 store misses |
| PAPI_L2_TCW | +8.94% | -6.58% | +6.02% | -0.37% | +9.87% | Level 2 total cache writes |
| PAPI_L2_DCW | +8.97% | -6.62% | +6.05% | -0.37% | +9.91% | Level 2 data cache writes |